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The Plasma CPU was created from scratch using VHDL (a hardware design language). It is compatible with the MIPS I(TM) instruction set. The Plasma CPU has 32 32-bit registers and is currently running at 25 MHz on a Xilinx FPGA.

The Plasma CPU is implemented in approximately 4000 lines of VHDL source code. The VHDL source code and additional documentation (including a block diagram) are available at the OpenCores website under the Plasma project.


Additional hardware blocks include:
  • UART
  • Interrupt Controller
  • Interrupt Timer
  • SRAM Controller
  • Flash Controller
  • DDR SDRAM Controller
  • Ethernet Media Access Controller (MAC)
This web site is running on a Spartan-3E Starter Kit with a Xilinx Spartan-3E FPGA, UART, 64 MB of DDR SDRAM, 16 MB flash, and an Ethernet PHY.

The Plasma CPU and web site can also run on the Spartan-3 Starter Kit Board which has a Xilinx Spartan-3 FPGA along with 1 MB of SRAM and a UART. The development board and the VHDL development tools can be purchased from Xilinx for $150. The FPGA alone costs less than $10 in large quantities.